H5TC2G83EFR-RDA
Description
The H5TC2G43EFR-xxA and H5TC2G83EFR-xxA are a 2Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.35V.
Key Features
- Fully differential clock inputs (CK, CK) operation
- Differential Data Strobe (DQS, DQS)
- Average Refresh Cycle (Tcase of0 oC~95oC) - 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC
- On chip DLL align DQ, DQS and DQS transition with CK
- DM masks write data-in at the both rising and falling edges of the data strobe
- All addresses and control inputs except data, data strobes and data masks latched on the rising edges of
- Programmable additive latency 0, CL-1, and CL-2 supported
- Write Levelization supported
- 8 bit pre-fetch
- This product in pliance with the RoHS directive
