H5TQ1G63AFP-xxC Datasheet Text
H5TQ1G43AFP-xxC H5TQ1G83AFP-xxC H5TQ1G63AFP-xxC
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1Gb DDR3 SDRAM
(Preliminary version)
H5TQ1G43AFP-xxC H5TQ1G83AFP-xxC H5TQ1G63AFP-xxC
- - Since DDR3 Specification has not been defined pletely yet in JEDEC, this document may contain items under discussion.
- - Contents may be changed at any time without any notice.
Rev. 0.1 / Nov 2007 This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied.
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H5TQ1G43AFP-xxC H5TQ1G83AFP-xxC H5TQ1G63AFP-xxC
Revision History
Revision No. 0.1 History Preliminary Draft Date 2007-11 Remark
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Rev. 0.1 /Nov 2007
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H5TQ1G43AFP-xxC H5TQ1G83AFP-xxC H5TQ1G63AFP-xxC
Table of Contents
1. Description 1.1 Device Features and Ordering Information 1.1.1 Description 1.1.2 Features
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1.1.3 Ordering Information 1.1.4 Ordering Frequency 1.2 Package Ballout 1.3 Row and Column Address Table : 512M/1G Fixed 1.4 Pin Functional Description 2. mand Description 2.1 mand Truth Table 2.2 Clock Enable (CKE) Truth Table for Synchronous Transitions 3....