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HC2510C - Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications

General Description

low-skew, low jitter, phaselocked loop(PLL) clock driver, distributing high frequency clock signals for SDRAM.

The HC2510C operates at 3.3V Vcc and provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

Key Features

  • l l l l l l l l l l l Phase-Locked Loop Clock Distribution for Synchronous DRAM.

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Datasheet Details

Part number HC2510C
Manufacturer SK Hynix
File Size 81.20 KB
Description Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications
Datasheet download datasheet HC2510C Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HC2510C HC2510C Features l l l l l l l l l l l Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specification Rev. 1.2” Distributes One Clock Input to One Bank of Ten Outputs No External RC Network Required External Feedback (FBIN) Pin is Used to Synchronize the Outputs to the Clock Input Separate Output Enable for Each Output Bank Operates at 3.