Phase-locked Loop Clock Distribution For Synchronous Dram Applications
| Part number | HC2509C |
|---|---|
| Manufacturer | SK Hynix |
| File Size | 84.01 KB |
| Description | Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications |
| Datasheet | HC2509C_HynixSemiconductor.pdf |
|
|
The HC2509C is a low-skew, low jitter, phase-locked loop(PLL) clock driver, distributing high frequency clock signals for SDRAM. The HC2509C operates at 3.3V Vcc and provides integrated series-damping resistors that make it ideal for driving point-to-point loads. The propagation delay from the CLK input to any clock output is nearly zero.
| Part Number | Description |
|---|---|
| HC2510 | Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications |
| HC2510C | Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications |
