HMT151R7AFP8C Datasheet | SK Hynix

Description 1.1 Device Features and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Key Parameters 1.3 Speed Grade 1.4 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1 1GB, 128Mx72 Module(1Rank of x8) 3.2 2GB, 256Mx72 Module(2Rank of x8) 3.3 2GB, 256Mx72 Module(1Rank of x4) 3.4 4GB, 512Mx72 Module(2Rank of x4) 3.5 4GB, 512Mx72 Module(4Rank of x8) 3.6 8GB, 1Gx72 Module(4Rank of x4) 4. Environment Parameter 5. Input/Output Capacitance & AC Parametrics 6. IDD Specifications 7. DIMM Outline Diagram 7.1 1GB, 128Mx72 Module(1Rank of x8) 7.2 2GB, 256Mx72 Module(2Rank of x8) 7.3 2GB, 256Mx72 Module(1Rank of x4) 7.4 4GB, 512Mx72 Module(2Rank of x4) 7.5 4GB, 512Mx72 Module(4Rank of x8) 7.6 8GB, 1Gx72 Module(4Rank of x4) Rev. 0.4 / Jul. 2009 .. 1. Description This Hynix DDR3 SDRAM Registered Dual In-Line Memory Module (DIMM) series consists of 1Gb A generation. These are intended for use as main memory in server and workstation systems, providing a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition. 1.1 Product Features & Ordering Information 1.1.1 Features - VDD=VDDQ=1.5V - VDDSPD=3.3V to 3.6V - Fully differential clock inputs (CK, CK) operation - Differential Data Strobe (DQS, DQS) - On chip DLL align DQ, DQS and /DQS transition with CK transition - DM masks write data-in at the both rising and falling edges of the data strobe - All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock - Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11) supported - Programmable additive latency 0, CL-1, and CL-2 sup ported - Programmable CAS Write latency (CWL) = 5, 6, 7, 8 - Programmable burst length 4/8 with both nibble sequential and interleave mode - BL switch on the fly - 8 banks - 8K refresh cycles /64ms - DDR3 SDRAM...