HY27SS16561M Datasheet | SK Hynix

description of Device Operations - /CE Don’t Care Enabled(Disabled) -> Sequential Row Read Disabled(Enabled) (Page23) 1) change FBGA dimension : Thickness : 1.2mm(max) -> 1.0mm(max) 2) Edit Fig.33 read operation with CE don't care 1) Change TSOP1,WSOP1,FBGA package dimension 0.6 - Change TSOP1,WSOP1,FBGA mechanical data - Inches parameter has been excluded from the mechanical data table 1) Change TSOP1, WSOP1, FBGA package dimension 2) Edit TSOP1, WSOP1 package figures 3) Change FBGA package figure Oct. 18. 2004 Preliminary History Draft Date Jul. 10. 2003 Dec. 08. 2003 Dec. 08. 2003 Remark Preliminary Preliminary Preliminary Mar. 08. 2004 Preliminary Jun. 01. 2004 Preliminary Sep. 24. 2004 Preliminary Oct. 20. 2004 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.7 / Oct. 2004 1 HY27SS(08/16)561M Series HY27US(08/16)561M Series 256Mbit (32Mx8bit / 16Mx16bit) NAND Flash FEATURES SUMMARY HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications FAST BLOCK ERASE - Block erase time: 2ms (Typ) NAND INTERFACE - x8 or x16 bus width. - Multiplexed Address/ Data .. - Pinout patibility for all densities STATUS REGISTER ELECTRONIC SIGNATURE SUPPLY VOLTAGE CHIP ENABLE DON'T CARE OPTION - Simple interface with microcontroller - 3.3V device: VCC = 2.7 to 3.6V : HY27USXX561M - 1.8V device: VCC = 1.7 to 1.95V : HY27SSXX561M AUTOMATIC PAGE 0 READ AT POWER-UP OPTION - Boot from NAND...