HY5DU12822ALT Overview
and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.0/Feb. 2003 1 .. HY5DU12422A(L)T HY5DU12822A(L)T HY5DU121622A(L)T Revision History 1. Rev 0.0 (Feb. 19)
HY5DU12822ALT Key Features
- VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are patible with SSTL_2 interface Fully differential clock inputs (CK,
- data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per ea
- Note : D of speed indicates DDR400