HY5DU12822AT Datasheet | SK Hynix

.. HY5DU12422A(L)T HY5DU12822A(L)T HY5DU121622A(L)T 512Mb DDR SDRAM HY5DU12422A(L)T HY5DU12822A(L)T HY5DU121622A(L)T This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.0/Feb. 2003 1 .. HY5DU12422A(L)T HY5DU12822A(L)T HY5DU121622A(L)T Revision History 1. Rev 0.0 (Feb. 19) 1) Datasheet Release in Preliminary version Rev. 0.0/Feb. 2003 .. HY5DU12422A(L)T HY5DU12822A(L)T HY5DU121622A(L)T DESCRIPTION PRELIMINARY The HY5DU12422A(L)T, HY5DU12822A(L)T and HY5DU121622A(L)T are a 536,870,912-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. This Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are patible with SSTL_2. Features - - - - - - - VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are patible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align DQ and DQS transition with CK transition DM mask write data-in at the both rising and falling edges of the data strobe - - - - - - - - - All addresses and control inputs except data, data...