HY5DU28422LT Datasheet PDF ((HY5DU28xxxAT) 3rd 128M DDR SDRAM) | Download Hynix Semiconductor HY5DU28422LT

HY5DU28422LT - (HY5DU28xxxAT) 3rd 128M DDR SDRAM

This page provides the datasheet information for the HY5DU28422LT, a member of the HY5DU28822AT (HY5DU28xxxAT) 3rd 128M DDR SDRAM family.

Description

and is subject to change without notice.

Hynix semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align DQ and DQS transition with CK transition DM mask write data-in at the both ri.

Datasheet Details

Part number	HY5DU28422LT
Manufacturer	SK Hynix
File Size	376.76 KB
Description	(HY5DU28xxxAT) 3rd 128M DDR SDRAM
Datasheet	HY5DU28422LT Datasheet
Additional preview pages of the HY5DU28422LT datasheet.

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Full PDF Text Transcription

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HY5DU28422A(L)T HY5DU28822A(L)T HY5DU281622A(L)T 3rd 128M DDR SDRAM HY5DU28422A(L)T HY5DU28822A(L)T HY5DU281622A(L)T This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/May. 02 1 www.DataSheet4U.com HY5DU28422A(L)T HY5DU28822A(L)T HY5DU281622A(L)T Revision History 1. Revision 0.2 (Nov.01) 1) Device operation and timing diagram removed 2) tHZ / tLZ SPEC defined 2. Revision 0.3 (Feb.02) 1) “Preliminary” removed 3. Revision 0.4 (May. 02) 1) Input leakage current changed from +/-5uA to +/-2uA Rev. 0.4/May.

Published: Mar 24, 2006 |