HY5DU28422LT Overview
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HY5DU28422LT Key Features
- VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are patible with SSTL_2 interface Fully differential clock inputs (CK,
- data transaction aligned to bidirectional data strobe (DQS) Data outputs on DQS edges when read (edged DQ) Data inputs o
- K -H -L
- X means speed grade -- JEDEC specification pliant