HY5DU28422T Datasheet PDF (2nd 128M DDR SDRAM) | Download Hynix Semiconductor HY5DU28422T

HY5DU28422T - 2nd 128M DDR SDRAM

Description

and is subject to change without notice.

128M DDR SDRAM Brief Information --------------------------------------------------------------------- 3 1.1 Description 1.2 Feature 1.3 Ordering Information 2.

Features

VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL ali.

Datasheet Details

Part number	HY5DU28422T
Manufacturer	SK Hynix
File Size	1.54 MB
Description	2nd 128M DDR SDRAM
Datasheet	HY5DU28422T Datasheet
Additional preview pages of the HY5DU28422T datasheet.

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Full PDF Text Transcription

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HY5DU28422T HY5DU28822T HY5DU281622T 2nd 128M DDR SDRAM HY5DU28422T HY5DU28822T HY5DU281622T Revision 1.3 April 2001 Rev. 1.3 / Apr. 2001 This document is a general product description and is subject to change without notice. 128Mb (x4, x8, x16) Double Data Rate SDRAM HY5DU28422T HY5DU28822T HY5DU281622T CONTENTS 1. 128M DDR SDRAM Brief Information --------------------------------------------------------------------- 3 1.1 Description 1.2 Feature 1.3 Ordering Information 2. Pin 2.1 2.2 2.3 & PKG Information --------------------------------------------------------------------------------------- 4 Pin Configuration Pin Description PKG Physical Dimension 3. Functional Block Diagram ----------------------------------------------------------------------------------- 7 4.

Published: Aug 4, 2014 |