HY5S2B6DLF-SE - 4Banks x 2M x 16bits Synchronous DRAM

This page provides the datasheet information for the HY5S2B6DLF-SE, a member of the HY5S2B6DLF-BE 4Banks x 2M x 16bits Synchronous DRAM family.

Product Overview

Hynix Semiconductor

Part number	HY5S2B6DLF-SE
Manufacturer	Hynix Semiconductor
File Size	791.81 KB
Description	4Banks x 2M x 16bits Synchronous DRAM
Datasheet	HY5S2B6DLF-SE Datasheet
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Standard SDR Protocol Internal 4bank operation.
Voltage : VDD = 1.8V, VDDQ = 1.8V.
LVCMOS compatible I/O Interface.
Low Voltage interface to reduce I/O power.
Low Power Features - PASR(Partial Array Self Refresh) - Auto TCSR (Temperature Compensated Self Refresh) - DS (Drive Strength) - Deep Power Down Mode.
Programmable CAS latency of 1, 2 or 3 Pakage Type : 54Ball FBGA - HY5S2B6DLF : Lead - HY5S2B6DLFP : Lead Free.

Other Datasheets by Hynix Semiconductor

Published: Mar 2, 2011 |