HY5S5B2CLFP-6E Datasheet | SK Hynix

description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.5 / Aug. 2008 1 256Mbit (8Mx32bit) Mobile SDR Memory HY5S5B2CLF(P) Series Document Title 4Bank x 2M x 32bits Synchronous DRAM Revision History Revision No. 0.1 0.2 1.0 1.1 1.2 Initial Draft Initial Draft Release Correct IDD5 value: 85m A max -> 110m A max Insert (Page11) DPD specification [IDD7: 10u A min] - Updated Auto Refresh cycle during Power-up and Initialization Sequence (8 cycles to 2 cycles) - Editorial changes in some descriptions - Corrected the description of BURST TERMINATE - Corrected the CJE state on every mand - Typo Corrected. History Draft Date Nov. 2006 Apr. 2007 June. 2007 June. 2007 July. 2007 Remark Preliminary Preliminary May 2008 1.4 1.5 Jun. 2008 Aug. 2008 Rev 1.5 / Aug. 2008 256Mbit (8Mx32bit) Mobile SDR Memory HY5S5B2CLF(P) Series DESCRIPTION The Hynix HY5S5B2CLF(P) is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, hand-held PCs. The Hynix 256M Mobile SDRAM is 268,435,456-bit CMOS Mobile Synchronous DRAM(Mobile SDR), ideally suited for the main memory applications which requires large memory density and high bandwidth. It is organized as 4banks of 2,097,152 x32. Mobile SDRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Mobile SDRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x16 Input/ Output bus. All the mands are latched in synchronization with the rising edge of CLK. The Mobile SDRAMs provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4, 8 locations or full page. An AUTO PRECHARGE function...