HY62U8100B Datasheet | SK Hynix

HY62U8100B Series 128Kx8bit CMOS SRAM Document Title 128K x8 bit 3.0V Low Power CMOS slow SRAM Revision History Revision No 10 History Initial Revision History Insert Revised - Insert 70ns Part Change the Notch Location of s TSOP - Left-Top => Left-Center Marking Information Add Revised - AC Test Condition Add : 5p F Test Load Changed Logo - HYUNDAI -> hynix - Marking Information Change Draft Date Jul.25.2000 Remark Final Sep.04.2000 Final Dec.04.2000 Final Apr.30.2001 Final .. This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 13 / Apr. 2001 Hynix Semiconductor HY62U8100B Series DESCRIPTION The HY62U8100B is a high speed, low power and 1M bit CMOS SRAM organized as 131,072 words by 8bit. The HY62U8100B uses high performance CMOS process technology and designed for high speed low power circuit technology. It is particulary well suited for used in high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 2.0V. Features - Fully static operation and Tri-state output - TTL patible inputs and outputs - Battery backup(LL-part) -. 2.0V(min) data retention - Standard pin configuration -. 32 - SOP - 525mil -. 32 -...