HY62U8400A Datasheet | SK Hynix

HY62U8400A Series 512Kx8bit CMOS SRAM Document Title 512K x8 bit 3.0V Low Power CMOS slow SRAM Revision History Revision No 04 History Revision History Insert Revised - Insert 70ns Part - Improved standby current Isb1 : 30u A ¡ æ 20u A Revised - Change Iccdr Value : 15u A => 20u A Marking Information Add Revised - E.T (-25~85°C), I.T (-40~85°C) Part Insert - AC Test Condition Add : 5p F Test Load - t CLZ Value Change : 15ns/20ns - > 10ns - VIH max : Vcc + 0.2V => Vcc + 0.3V - VIL min : - 0.2V => - 0.3V Changed Logo - HYUNDAI -> hynix - Marking Information Change Draft Date Jul.26.2000 Remark Final 05 06 Aug.04.2000 Dec.04.2000 Final Final Apr.30.2001 Final .. This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 07 / Apr. 2001 Hynix Semiconductor HY62U8400A Series DESCRIPTION The HY62U8400A is a high-speed, low power and 4M bits CMOS SRAM organized as 512K words by 8 bits. The HY62U8400A uses Hynix's high performance twin tub CMOS process technology and was designed for high-speed and low power circuit technology. It is particularly well suited for use in high-density and low power system applications. This device has a data retention mode that guarantees data to remain valid at the minimum power supply voltage of...