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HY67V161610D - 2 Banks x 512K x 16 Bit Synchronous DRAM

General Description

and is subject to change without notice.

Hyundai Electronics does not assume any responsibility for use of circuits described.

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Key Features

  • Single 3.0V to 3.6V power supply Note1).
  • Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 and Full Page for Sequence Burst All device pins are compatible with LVTTL interface JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin pitch.
  • All inputs and outputs referenced to positive edge of system clock - 1, 2, 4 and 8 for Interleave Burst.
  • Programmable C.

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Datasheet Details

Part number HY67V161610D
Manufacturer SK Hynix
File Size 101.43 KB
Description 2 Banks x 512K x 16 Bit Synchronous DRAM
Datasheet download datasheet HY67V161610D Datasheet

Full PDF Text Transcription for HY67V161610D (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for HY67V161610D. For precise diagrams, and layout, please refer to the original PDF.

www.DataSheet4U.com HY57V161610D 2 Banks x 512K x 16 Bit Synchronous DRAM D E S C R IP T IO N THE Hyundai HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally...

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undai HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic applications which require large memory density and high bandwidth. HY57V161610D is organized as 2banks of 524,288x16. HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

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