HY5PS561621ALFP Datasheet | SK Hynix

description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4 / Sep. 2006 1 1 1HY5PS561621A(L)FP Revision History Rev. 0.1 Initial data sheet release. Removed all contents on x4/8 Org. Updated IDD Spec. Removed improper note in ODT DC spec. Timing Parameters Table Modified History Draft Date June. 2005 Oct. 2005 .. 0.3 0.4 July 2006 Sep. 2006 Rev. 0.4 / Sep. 2006 1 1HY5PS561621A(L)FP Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Key Feaures 1.1.2 Ordering Information 1.1.3 Ordering Frequency 1.2 Pin configuration .. 1.3 Pin Description 2. Maximum DC ratings 2.1 Absolute Maximum DC Ratings 2.2 Operating Temperature Condition 3. AC & DC Operating Conditions 3.1 DC Operating Conditions 5.1.1 Remended DC Operating Conditions(SSTL_1.8) 5.1.2 ODT DC Electrical Characteristics 3.2 DC & AC Logic Input Levels 3.2.1 Input DC Logic Level 3.2.2 Input AC Logic Level 3.2.3 AC Input Test Conditions 3.2.4 Differential Input AC Logic Level 3.2.5 Differential AC output parameters 3.3 Output Buffer Levels 3.3.1 Output AC Test Conditions 3.3.2 Output DC Current Drive 3.3.3 OCD default chracteristics 3.4 IDD Specifications & Measurement Conditions 3.5 Input/Output Capacitance 4. AC Timing Specifications 5. Package Dimensions Rev. 0.4 / Sep. 2006 1 1HY5PS561621A(L)FP 1. Description 1.1 Device Features & Ordering Information 1.1.1 Key Features - VDD ,VDDQ =1.8 +/- 0.1V - All inputs and outputs are patible with SSTL_18 interface - Fully differential clock inputs (CK, /CK) operation .. - Double data rate interface - Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) - Data outputs on DQS, DQS edges when read (edged DQ) - Differential Data Strobe (DQS, DQS) - Data inputs on DQS centers when write(centered DQ) - On chip DLL align DQ, DQS and DQS transition with CK transition - DM mask...