HY5PS56421LF Datasheet | SK Hynix

description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0/ July. 2004 1 HY5PS56421(L)F HY5PS56821(L)F HY5PS561621(L)F Revision History Rev. 0.1 0.2 0.3 ..1.0 History Initial Release Editorial clean up, changed t RAS spec. for DDR2 400 1) Defined IDD Spec. 2) Added Speed bins table in AC timming specification Transfered Functional description , mand truth table pages and Some contents of Operating conditions to <Device Operation & timing diagram> Draft Date Dec. 2003 Jan. 2004 May 2004 Jul. 2004 Rev 1.0/July. 2004 HY5PS56421(L)F HY5PS56821(L)F HY5PS561621(L)F Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Key Feaures 1.1.2 Ordering Information 1.1.3 Ordering Frequency 1.2 Pin configuration 1.3 Pin Description .. 2. Maximum DC ratings 2.1 Absolute Maximum DC Ratings 2.2 Operating Temperature Condition 3. AC & DC Operating Conditions 3.1 DC Operating Conditions 5.1.1 Remended DC Operating Conditions(SSTL_1.8) 5.1.2 ODT DC Electrical Characteristics 3.2 DC & AC Logic Input Levels 3.2.1 Input DC Logic Level 3.2.2 Input AC Logic Level 3.2.3 AC Input Test Conditions 3.2.4 Differential Input AC Logic Level 3.2.5 Differential AC output parameters 3.3 Output Buffer Levels 3.3.1 Output AC Test Conditions 3.3.2 Output DC Current Drive 3.3.3 OCD default chracteristics 3.4 IDD Specifications & Measurement Conditions 3.5 Input/Output Capacitance 4. AC Timing Specifications 5. Package Dimensions Rev 1.0 / July. 2004 HY5PS56421(L)F HY5PS56821(L)F HY5PS561621(L)F 1. Description 1.1 Device Features & Ordering Information 1.1.1 Key Features - - .. - - - - - - - - - - - - - - - - - - - - - - - VDD=1.8V VDDQ=1.8V +/- 0.1V All inputs and outputs are patible with SSTL_18 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous-data transaction aligned to bidirectional data strobe...