HYMP512Rxxx
FEATURES
- JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply
- All inputs and outputs are patible with SSTL_1.8 interface
- -
- -
- 4 Bank architecture Posted CAS Programmable CAS Latency 3 , 4 , 5 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination)
- -
- -
- -
- - Fully differential clock operations (CK & CK) Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60ball FBGA 133.35 x 30.00 mm form factor Lead-free Products are Ro HS pliant
ORDERING INFORMATION
Part Name HYMP564R728-E3/C4 HYMP512R728-E3/C4 HYMP512R724-E3/C4 HYMP125R72M4-E3/C4 HYMP564R72P8-E3/C4 HYMP512R72P8-E3/C4 HYMP512R72P4-E3/C4 HYMP125R72MP4-E3/C4 Density 512MB 1GB 1GB 2GB 512MB 1GB 1GB 2GB Organization 64Mx72 128Mx72 128Mx72 256Mx72 64Mx72 128Mx72 128Mx72 256Mx72 # of DRAMs 9 18 18 36 9 18 18 36 # of ranks 1 2 1 2...
