HYMP512Rxxx Description
and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied.
HYMP512Rxxx Key Features
- JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply
- All inputs and outputs are patible with SSTL_1.8 interface
- 4 Bank architecture Posted CAS Programmable CAS Latency 3 , 4 , 5 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die
- Fully differential clock operations (CK & CK) Programmable Burst Length 4 / 8 with both sequential and interleave mode A