Datasheet Details
| Part number | HYMP512Uxxx |
|---|---|
| Manufacturer | SK Hynix |
| File Size | 442.92 KB |
| Description | DDR2 SDRAM Unbuffered DIMMs Based on 512M |
| Datasheet |
 HYMP512Uxxx Datasheet
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General Description
and is subject to change without notice.
Hynix Semiconductor does not assume any responsibility for use of circuits described.
No patent licenses are implied.
Key Features
- JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 4 Bank architecture Posted CAS Programmable CAS Latency 3 , 4 , 5 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination).
- Fully differential clock operations (CK & CK) Programmable Burst Length 4 / 8 with both sequential and interleave mode.