HYMP512Uxxx
FEATURES
- JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply All inputs and outputs are patible with SSTL_1.8 interface 4 Bank architecture Posted CAS Programmable CAS Latency 3 , 4 , 5 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination)
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- - Fully differential clock operations (CK & CK) Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60ball FBGA(64Mx8), 84ball FBGA(32Mx16) 133.35 x 30.00 mm form factor Lead-free Products are Ro HS pliant
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ORDERING INFORMATION
Part Name HYMP532U646-E3/C4 HYMP564U648-E3/C4 HYMP564U728-E3/C4 HYMP512U648-E3/C4 HYMP512U728-E3/C4 HYMP532U64P6-E3/C4 HYMP564U64P8-E3/C4 HYMP564U72P8-E3/C4 HYMP512U64P8-E3/C4 HYMP512U72P8-E3/C4 Density 256MB 512MB 512MB 1GB 1GB 256MB 512MB 512MB 1GB 1GB Organization 32Mx64 64Mx64 64Mx72 128Mx64...
