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AiP74HCT595 - Serial or Parallel-out Shift Register

This page provides the datasheet information for the AiP74HCT595, a member of the AiP74HC595-I Serial or Parallel-out Shift Register family.

Datasheet Summary

Description

2012-06-A1 2012-06 New 2021-09-A2 2021-09 Modify Ordering Information 2021-12-A3 2021-12 Modify Ordering Information 2022-01-A4 2022-01 Modify ambient temperature to -40℃~+105℃ and add electrical characteristics of -40℃~+105℃ 2022-08-A5 2022-08 Modify the tube packing specifications of SOP1

Features

  • a serial input.
  • (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage i-core.
  • register. Data in t.

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Datasheet preview – AiP74HCT595

Datasheet Details

Part number AiP74HCT595
Manufacturer I-CORE
File Size 937.92 KB
Description Serial or Parallel-out Shift Register
Datasheet download datasheet AiP74HCT595 Datasheet
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Full PDF Text Transcription

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Wuxi I-CORE Electronics Co., Ltd.
Published: |