DESCRIPTION
2019-07-A1 2019-07 New 2023-04-B1 2023-04 Update the template Address：Building B4,NO.777,Jianzhu Road,Binhu District,Wuxi City,Jiangsu Province cn P.C.：214072 1/ 17 VER：2023-04-B1 Wuxi I-CORE Electronics Co., Ltd. Tab: 835-12-B4 Number:CD4017-AX-LJ-D005EN 1、GENERAL DESCRIPTION
— The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or a — HIGH-to-LOW transition at CP1 while CP0 is HIGH. i-core — When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5, 6, 7, 8, and 9, — can be used to drive the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0=Q — 5-9=HIGH; Q1 to Q9=LOW) independent of the clock inputs (CP0, CP1). Automatic counter code correction is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses. It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.
I-CORE
