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ICS548-03 Datasheet Low Skew Clock Inverter And Divider

Manufacturer: ICST

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Datasheet Details

Part number ICS548-03
Manufacturer ICST
File Size 85.04 KB
Description Low Skew Clock Inverter and Divider
Datasheet ICS548-03_ICST.pdf

General Description

The ICS548-03 is a low cost, low skew, high performance general-purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-2.

Using our patented analog Phase-Locked Loop (PLL) techniques, the device operates from a frequency range from 10 MHz to 120 MHz in the PLL mode, and up to 160 MHz in the non-PLL mode.

In applications that to need maintain low phase noise in the clock tree, the non-PLL (when S3=S2=1) mode should be used.

Key Features

  • Packaged in 16 pin narrow (150 mil) SOIC Input clock up to 160 MHz in the non-PLL mode Provides clock outputs of CLK, CLK, and CLK/2 Low skew (500 ps) on CLK, CLK, and CLK/2 All outputs can be tri-stated Entire chip can be powered down by changing one or two select pins.
  • 3.3V or 5.0V operating voltage.

Similar Datasheet

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