Datasheet4U Logo Datasheet4U.com

ICS85314-01 - LVPECL FANOUT BUFFER

Description

The ICS85314-01 is a low skew, high performance 1-to-5 Differential-to-3.3V LVPECL fanout buffer HiPerClockS™ and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS.

The ICS85314-01 has two selectable clock inputs.

Features

  • 5 differential 2.5V/3.3V LVPECL outputs.
  • Selectable differential CLK0, nCLK0 or LVCMOS inputs.
  • CLK0, nCLK0 pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL.
  • CLK1 can accept the following input levels: LVCMOS or LVTTL.
  • Maximum output frequency: 650MHz.
  • Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input.
  • Output skew: 50ps (maximum).
  • Part-to-.

📥 Download Datasheet

Datasheet preview – ICS85314-01

Datasheet Details

Part number ICS85314-01
Manufacturer ICST
File Size 134.61 KB
Description LVPECL FANOUT BUFFER
Datasheet download datasheet ICS85314-01 Datasheet
Additional preview pages of the ICS85314-01 datasheet.

📁 Similar Datasheet

  • ICS8530-01 - Differential-to-3.3V LVPECL Fanout Buffer (Integrated Device Technology)
  • ICS853052 - DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL LVPECL MULTIPLEXER (IDT)
  • ICS8530I-01 - 1-To-16 Differentail-To-3.3V LVPECL Fanout Buffer (Integrated Device Technology)
  • ICS8536-01 - 1-to-6 Crystal / LVCMOS / Differential-to-3.3V / 2.5V LVPECL Fanout Buffer (Integrated Device Technology)
  • ICS853S006I - LVPECL/ECL Fanout Buffer (IDT)
  • ICS853S006I - LVPECL/ECL Fanout Buffer (Renesas)
  • ICS853S011BI - LVPECL/ECL Fanout Buffer (IDT)
  • ICS853S011CI - LVPECL/ECL Fanout Buffer (IDT)
  • ICS853S012I - LVPECL Clock/Data Multiplexer (IDT)
  • ICS853S012I - LVPECL Clock/Data Multiplexer (Renesas)
Other Datasheets by ICST

Full PDF Text Transcription

Click to expand full text
www.DataSheet4U.com PRELIMINARY Integrated Circuit Systems, Inc. ICS85314-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER FEATURES • 5 differential 2.5V/3.3V LVPECL outputs • Selectable differential CLK0, nCLK0 or LVCMOS inputs • CLK0, nCLK0 pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 650MHz • Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input • Output skew: 50ps (maximum) • Part-to-part skew: 400ps (maximum) • Propagation delay: CLK0, nCLK0 - 2.1ns (maximum) CLK1 - 2.1ns (maximum) • LVPECL mode operating voltage supply range: VCC = 2.375V to 3.
Published: |