9DBL02 - 2-output 3.3V PCIe Zero-Delay Buffer

IDT

General Description

The 9DBL02 devices are 3.3V members of IDT's Full-Featured PCIe family.

The devices support PCIe Gen1-4 Common Clocked (CC) and PCIe Gen2 Separate Reference Independent Spread (SRIS) systems.

Key Features

2.
1-200 MHz Low-Power (LP) HCSL DIF pairs.
9DBL0242 default ZOUT = 100.
9DBL0252 default ZOUT = 85.
9DBL02P2 factory programmable defaults.
Easy AC-coupling to other logic families, see IDT.

📥 Download Datasheet

9DBL02 2-output 3.3v pcie zero-delay buffer by IDT - Datasheet Preview

Datasheet Details

Part number	9DBL02
Manufacturer	IDT
File Size	288.27 KB
Description	2-output 3.3V PCIe Zero-Delay Buffer
Datasheet	9DBL02 Datasheet

📁 Similar Datasheet

Part Number	Description	Manufacturer
9DBL0242	Zero-Delay/Fanout Buffer	Renesas
9DBL0242C	2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers	Renesas
9DBL0252	Zero-Delay/Fanout Buffer	Renesas
9DBL0252C	2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers	Renesas
9DBL0255	2 and 4-Output 3.3V PCIe Gen1-5 Clock Fanout Buffers	Renesas

Other Datasheets by IDT

Part Number	Description
9DBL0242	2-output 3.3V PCIe Zero-Delay Buffer
9DBL0243	2-Output 3.3V LP-HCSL Zero-Delay Buffer
9DBL0252	2-output 3.3V PCIe Zero-Delay Buffer
9DBL0253	2-Output 3.3V LP-HCSL Zero-Delay Buffer
9DBL0255	PCIe Gen1-5 Clock Fanout Buffers

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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2-output 3.3V PCIe Zero-Delay Buffer 9DBL02 Description The 9DBL02 devices are 3.3V members of IDT's Full-Featured PCIe family. The devices support PCIe Gen1-4 Common Clocked (CC) and PCIe Gen2 Separate Reference Independent Spread (SRIS) systems. It offers a choice of integrated output terminations providing direct connection to 85 or 100 transmission lines. The 9DBL02P1 can be factory programmed with a user-defined power up default SMBus configuration.