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9DBL0851 - 8-output 3.3V PCIe Zero-Delay Buffer

This page provides the datasheet information for the 9DBL0851, a member of the 9DBL0841 8-output 3.3V PCIe Zero-Delay Buffer family.

Datasheet Summary

Description

The 9DBL0841 / 9DBL0851 devices are 3.3V members of IDT's Full-Featured PCIe family.

The 9DBL0841 / 9DBL0851 supports PCIe Gen1-4 Common Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems.

Features

  • 8.
  • 1-200 MHz Low-Power (LP) HCSL DIF pairs.
  • 9DBL0841 default ZOUT = 100.
  • 9DBL0851 default ZOUT = 85.
  • 9DBL08P1 factory programmable defaults.
  • Easy AC-coupling to other logic families, see IDT.

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Datasheet preview – 9DBL0851

Datasheet Details

Part number 9DBL0851
Manufacturer IDT
File Size 333.43 KB
Description 8-output 3.3V PCIe Zero-Delay Buffer
Datasheet download datasheet 9DBL0851 Datasheet
Additional preview pages of the 9DBL0851 datasheet.

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Full PDF Text Transcription

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8-output 3.3V PCIe Zero-Delay Buffer 9DBL0841 / 9DBL0851 Description The 9DBL0841 / 9DBL0851 devices are 3.3V members of IDT's Full-Featured PCIe family. The 9DBL0841 / 9DBL0851 supports PCIe Gen1-4 Common Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems. It offers a choice of integrated output terminations providing direct connection to 85Ω or 100Ω transmission lines. The 9DBL08P1 can be factory programmed with a user-defined power up default SMBus configuration.
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