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9DBL0853 - LP-HCSL Zero-Delay Buffer

This page provides the datasheet information for the 9DBL0853, a member of the 9DBL0843 LP-HCSL Zero-Delay Buffer family.

Datasheet Summary

Description

The 9DBL08x3 devices are 3.3V members of IDT's Full-Featured PCIe clock family.

They support PCIe Gen1-4 Common Clock (CC) architectures and also support NVLINK applications.

The 9DBL08x3 parts have a Loss of Signal (LOS) indicator to support fault-tolerant, high reliability systems.

Features

  • Loss Of Signal (LOS) open drain output.
  • 8.
  • 1-200 MHz Low-Power (LP) HCSL DIF pairs.
  • 9DBL0843 default Zout = 100Ω.
  • 9DBL0853 default Zout = 85Ω.
  • Easy AC-coupling to other logic families, see IDT.

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Datasheet preview – 9DBL0853

Datasheet Details

Part number 9DBL0853
Manufacturer Renesas
File Size 495.28 KB
Description LP-HCSL Zero-Delay Buffer
Datasheet download datasheet 9DBL0853 Datasheet
Additional preview pages of the 9DBL0853 datasheet.

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Full PDF Text Transcription

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8-output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator 9DBL08x3 Datasheet General Description The 9DBL08x3 devices are 3.3V members of IDT's Full-Featured PCIe clock family. They support PCIe Gen1-4 Common Clock (CC) architectures and also support NVLINK applications. The 9DBL08x3 parts have a Loss of Signal (LOS) indicator to support fault-tolerant, high reliability systems. Recommended Application PCIe Gen1-4 and NVLINK clock distribution for Riser Cards, Storage, Networking, JBOD, Communications, Access Points Output Features ▪ Loss Of Signal (LOS) open drain output ▪ 8 – 1-200 MHz Low-Power (LP) HCSL DIF pairs ▪ 9DBL0843 default Zout = 100Ω ▪ 9DBL0853 default Zout = 85Ω ▪ Easy AC-coupling to other logic families, see IDT application note AN-891.
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