9DBU0241 Key Features
- 1-167MHz Low-Power (LP) HCSL DIF pairs
- DIF cycle-to-cycle jitter <50ps
- DIF output-to-output skew <50ps
- DIF phase jitter is PCIe Gen1-2-3 pliant
- Direct connection to 100 transmission lines; saves 8
- 35mW typical power consumption in PLL mode; eliminates
- Spread Spectrum (SS) patible