9DBU0531 Key Features
- 1-167MHz Low-Power (LP) HCSL DIF pairs
- DIF additive cycle-to-cycle jitter <5ps
- DIF output-to-output skew <60ps
- DIF additive phase jitter is <300fs rms for PCIe Gen3
- DIF additive phase jitter <350s rms for SGMII
- LP-HCSL outputs; save 10 resistors pared to standard
- 35mW typical power consumption; eliminates thermal
- Spread Spectrum (SS) patible; allows SS for EMI
- OE# pins for each output; support DIF power management
- HCSL-patible differential input; can be driven by