9DBU0841 Key Features
- 1-167MHz Low-Power (LP) HCSL DIF pairs
- DIF cycle-to-cycle jitter <50ps
- DIF output-to-output skew < 80ps
- DIF phase jitter is PCIe Gen1-2-3 pliant
- Very low additive phase jitter in bypass mode
- Direct connection to 100 transmission lines; saves 32
- 53mW typical power consumption in PLL mode; eliminates
- Outputs can optionally be supplied from any voltage