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9FGL0251 - 2-Output 3.3V PCIe Clock Generator

This page provides the datasheet information for the 9FGL0251, a member of the 9FGL0241 2-Output 3.3V PCIe Clock Generator family.

Datasheet Summary

Description

The 9FGL0241 / 9FGL0251 devices are 2-output clock generators in IDT's 3.3V Full-Featured PCIe family.

Each output has a dedicated OE# pin for clock management.

Two different spread spectrum levels in addition to spread off are supported.

4 Common C

Features

  • Two 100MHz Low-Power HCSL (LP-HCSL) DIF output pairs:.
  • 9FGL0241 default Zout = 100Ω.
  • 9FGL0251 default Zout = 85Ω.
  • One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) support.
  • See AN-891 for easy AC-coupling to other logic families Key Specifications.
  • PCIe Gen1.
  • 4 CC compliant; Gen2.
  • 3 SRIS compliant.
  • DIF cycle-to-c.

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Datasheet preview – 9FGL0251

Datasheet Details

Part number 9FGL0251
Manufacturer IDT
File Size 312.39 KB
Description 2-Output 3.3V PCIe Clock Generator
Datasheet download datasheet 9FGL0251 Datasheet
Additional preview pages of the 9FGL0251 datasheet.

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Full PDF Text Transcription

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2-Output 3.3V PCIe Clock Generator 9FGL0241 / 9FGL0251 Datasheet Description The 9FGL0241 / 9FGL0251 devices are 2-output clock generators in IDT's 3.3V Full-Featured PCIe family. Each output has a dedicated OE# pin for clock management. Two different spread spectrum levels in addition to spread off are supported. The 9FGL0241 / 9FGL0251 supports PCIe Gen1–4 Common Clocked architectures (CC) and PCIe Separate Reference no-Spread (SRnS) and Separate Reference Independent Spread (SRIS) clocking architectures. Typical Applications ▪ Servers/High-Performance Computing/Accelerators ▪ Storage ▪ Embedded Systems/Industrial Control Output Features ▪ Two 100MHz Low-Power HCSL (LP-HCSL) DIF output pairs: • 9FGL0241 default Zout = 100Ω • 9FGL0251 default Zout = 85Ω ▪ One 3.
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