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9FGL0451 - 4-Output 3.3V PCIe Clock Generator

Download the 9FGL0451 datasheet PDF. This datasheet also covers the 9FGL0441 variant, as both devices belong to the same 4-output 3.3v pcie clock generator family and are provided as variant models within a single manufacturer datasheet.

General Description

The 9FGL0441 / 9FGL0451 devices are 4-output clock generators in IDT's 3.3V Full-Featured PCIe family.

Each output has a dedicated OE# pin for clock management.

Two different spread spectrum levels in addition to spread off are supported.

4 Common C

Key Features

  • Four 100MHz Low-Power HCSL (LP-HCSL) DIF pairs:.
  • 9FGL0441 default Zo = 100Ω.
  • 9FGL0451 default Zo = 85Ω.
  • One 3.3V LVCMOS REF output; Wake-On-LAN (WOL) support.
  • See AN-891 for easy AC-coupling to other logic families Key Specifications.
  • PCIe Gen1.
  • 4 CC compliant; Gen2.
  • 3 SRIS compliant.
  • DIF cycle-to-cycle jitter <.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (9FGL0441-IDT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 9FGL0451
Manufacturer IDT
File Size 317.35 KB
Description 4-Output 3.3V PCIe Clock Generator
Datasheet download datasheet 9FGL0451 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
4-Output 3.3V PCIe Clock Generator 9FGL0441 / 9FGL0451 Datasheet Description The 9FGL0441 / 9FGL0451 devices are 4-output clock generators in IDT's 3.3V Full-Featured PCIe family. Each output has a dedicated OE# pin for clock management. Two different spread spectrum levels in addition to spread off are supported. The 9FGL0441 / 9FGL0451 supports PCIe Gen1–4 Common Clocked architectures (CC) and PCIe Separate Reference no-Spread (SRnS) and Separate Reference Independent Spread (SRIS) clocking architectures. Typical Applications ▪ Servers/High-Performance Computing/Accelerators ▪ Storage ▪ Embedded Systems/Industrial Control Output Features ▪ Four 100MHz Low-Power HCSL (LP-HCSL) DIF pairs: • 9FGL0441 default Zo = 100Ω • 9FGL0451 default Zo = 85Ω ▪ One 3.