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DAC1617D1G0 - Dual 16-bit DAC

General Description

The DAC1617D1G0 is a high-speed 16-bit dual channel Digital-to-Analog Converter (DAC) with selectable ×2, ×4 and ×8 interpolation filters.

The device is optimized for multi-carrier and broadband wireless transmitters at sample rates of up to 1 Gsps.

Key Features

  • Dual-channel 16-bit resolution 1 Gsps maximum update rate Selectable ×2, ×4 and ×8 interpolation filters Very low noise capacitor-free integrated Phase-Locked Loop (PLL) Embedded Numerically Controlled Oscillator (NCO) with 40-bit programmable frequency Embedded complex(I/Q) digital IF modulator 1.8 V and 3.3 V power supplies LVDS DDR compatible input interface with on-chip 100 Ω terminations LVDS DDR input clock up to 370 MHz LVDS or LVPECL compatible DAC clock Interleaved or folded I and Q da.

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Datasheet Details

Part number DAC1617D1G0
Manufacturer IDT
File Size 852.47 KB
Description Dual 16-bit DAC
Datasheet download datasheet DAC1617D1G0 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DAC1617D1G0 Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating Rev. 4 — 12 December 2012 Product data sheet 1. General description The DAC1617D1G0 is a high-speed 16-bit dual channel Digital-to-Analog Converter (DAC) with selectable ×2, ×4 and ×8 interpolation filters. The device is optimized for multi-carrier and broadband wireless transmitters at sample rates of up to 1 Gsps. Supplied from a 3.3 V and a 1.8 V source, the DAC1617D1G0 integrates a differential scalable output current up to 34 mA. The Serial Peripheral Interface (SPI) provides full control of the DAC1617D1G0. The DAC1617D1G0 integrates a Low Voltage Differential Signaling (LVDS) Double Data Rate (DDR) receiver interface, with an on-chip 100 Ω termination.