DAC1653D Datasheet | IDT

DESCRIPTION DAC1653D and DAC1658D are high-speed, high-performance 16-bit dual channel Digital-to-Analog Converters (DACs). The devices provide sample rates up to 2 Gsps with selectable 2, 4 and 8 interpolation filters optimized for multi-carrier and broadband wireless transmitters. When both devices are referred to in this data sheet, the following convention will be used: DAC165x D. The DAC165x D integrates a JEDEC JESD204B patible high-speed serial input data interface running up to 10 Gbps allowing dual channel input sampling at up to 1 Gsps over four differential lanes. It offers numerous advantages over traditional parallel digital interfaces: - Easier Printed-Circuit Board (PCB) layout - Lower radiated noise - Lower pin count - Self-synchronous link - Skew pensation - Deterministic latency - Multiple Device Synchronization (MDS); JESD204B subclass 1 patible - Harmonic clocking support - Assured FPGA interoperability There are two versions of the DAC165x D: - Low mon-mode output voltage (part identification DAC1653D) - High mon-mode output voltage (part identification DAC1658D) An optional on-chip digital modulator converts the plex I/Q pattern from baseband to IF. The mixer frequency is set by writing to the Serial Peripheral Interface (SPI) control registers associated with the on-chip 40-bit Numerically Controlled Oscillator (NCO). This accurately places the IF carrier in the frequency domain. The 13-bit phase adjustment feature , the 12-bit digital gain and the 16-bit digital offset enable full control of the analog output signals. The DAC165x D is fully patible with device subclass 1 of the JEDEC JESD204B standard, guaranteeing deterministic and repeatable interface latency using the differential SYSREF signal. The device also supports harmonic clocking to reduce system-level clock synthesis and distribution challenges. Multiple Device Synchronization (MDS) enables multiple DAC channels to be sample synchronous and phase coherent to within one DAC clock...