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ICS854S01I - 2:1 Differential-to-LVDS Multiplexer

General Description

The ICS854S01I is a high performance 2:1 Differential-to-LVDS Multiplexer.

The ICS854S01I can also perform differential translation because the differential inputs accept LVPECL, LVDS or CML levels.

Key Features

  • 2:1 LVDS MUX.
  • One LVDS output pair.
  • Two differential clock inputs can accept: LVPECL, LVDS, CML.
  • Maximum input/output frequency: 2.5GHz.
  • Translates LVCMOS/LVTTL input signals to LVDS levels by using a resistor bias network on nPCLK0, nPCLK1.
  • RMS additive phase jitter: 0.06ps (typical).
  • Propagation delay: 600ps (maximum).
  • Part-to-part skew: 350ps (maximum).
  • Full 3.3V supply mode.
  • -40°C to 85°C ambient opera.

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Datasheet Details

Part number ICS854S01I
Manufacturer IDT
File Size 288.38 KB
Description 2:1 Differential-to-LVDS Multiplexer
Datasheet download datasheet ICS854S01I Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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2:1 Differential-to-LVDS Multiplexer ICS854S01I DATASHEET General Description The ICS854S01I is a high performance 2:1 Differential-to-LVDS Multiplexer. The ICS854S01I can also perform differential translation because the differential inputs accept LVPECL, LVDS or CML levels. The ICS854S01I is packaged in a small 3mm x 3mm 16 VFQFN package, making it ideal for use on space constrained boards. Features • 2:1 LVDS MUX • One LVDS output pair • Two differential clock inputs can accept: LVPECL, LVDS, CML • Maximum input/output frequency: 2.5GHz • Translates LVCMOS/LVTTL input signals to LVDS levels by using a resistor bias network on nPCLK0, nPCLK1 • RMS additive phase jitter: 0.06ps (typical) • Propagation delay: 600ps (maximum) • Part-to-part skew: 350ps (maximum) • Full 3.