IDT70P34L Datasheet | IDT

.. HIGH-SPEED 1.8V 8/4K x 18 DUAL-PORT 8/4K x 16 DUAL-PORT STATIC RAM Features - - ADVANCED IDT70P35/34L IDT70P25/24L - - - True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access IDT70P35/34L (IDT70P25/24L) - mercial: 20/25ns (max.) - Industrial: 25ns (max.) Low-power operation IDT70P35/34L (IDT70P25/24L) Active: 30.6m W (typ.) Standby: 5.4m W (typ.) Separate upper-byte and lower-byte control for multiplexed bus patibility IDT70P35/34L (IDT70P25/24L) easily expands data bus width to 36 bits (32 bits) or more using the Master/Slave - - - - - - - - select when cascading more than one device M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave BUSY and Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port LVTTL-patible, single 1.8V (±100m V) power supply Available in a 100-pin Thin Quad Flatpack (TQFP) package, 100-pin 0.8mm pitch Ball Grid Array (fp BGA), and 100-pin 0.5mm pitch BGA (fp BGA) Industrial temperature range (-40°C to +85°C) is available for selected speeds Functional Block Diagram R/WL UBL R/WR UBR LB L CEL OEL LBR CER OER , I/O9L-I/O17L(5) I/O0L-I/O8L(4) BUSYL A12L(1) A0L (2,3) I/O9R-I/O17R(5) I/O Control I/O Control I/O0R-I/O8R(4) BUSYR (2,3) Address Decoder MEMORY ARRAY Address Decoder A12R(1) A0R CEL OEL R/WL SEML (3) INTL NOTES: 1. A12 is a NC for IDT70P34 and IDT70P24. 2. (MASTER): BUSY is output; (SLAVE): BUSY is input. 3. BUSY outputs and INT outputs are non-tri-stated push-pull. 4. I/O0x - I/O 7x for IDT70P25/24. 5. I/O8x - I/O15 x for IDT70P25/24. ARBITRATION INTERRUPT SEMAPHORE LOGIC CER OER R/WR SEMR...