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IDT71V547XS - 3.3V Synchronous SRAM

This page provides the datasheet information for the IDT71V547XS, a member of the IDT71V547S 3.3V Synchronous SRAM family.

Features

  • 128K x 36 memory configuration, flow-through outputs.
  • Supports high performance system speed - 95 MHz (8ns Clock-to-Data Access).
  • ZBTTM Feature - No dead cycles between write and read cycles.
  • Internally synchronized signal eliminates the need to control OE Functional Block Diagram LBO Address A [0:16] CE1, CE2, CE2 R/W CEN ADV/LD BWx DQ DQ.
  • Single R/W (READ/WRITE) control pin.
  • 4-word burst capability (Interleaved or linear).
  • Individual byte write (BW1 - BW4.

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Datasheet preview – IDT71V547XS

Datasheet Details

Part number IDT71V547XS
Manufacturer IDT
File Size 696.98 KB
Description 3.3V Synchronous SRAM
Datasheet download datasheet IDT71V547XS Datasheet
Additional preview pages of the IDT71V547XS datasheet.

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Full PDF Text Transcription

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128K X 36, 3.3V Synchronous IDT71V547S/XS SRAM with ZBT™ Feature, Burst Counter and Flow-Through Outputs Features ◆ 128K x 36 memory configuration, flow-through outputs ◆ Supports high performance system speed - 95 MHz (8ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized signal eliminates the need to control OE Functional Block Diagram LBO Address A [0:16] CE1, CE2, CE2 R/W CEN ADV/LD BWx DQ DQ ◆ Single R/W (READ/WRITE) control pin ◆ 4-word burst capability (Interleaved or linear) ◆ Individual byte write (BW1 - BW4) control (May tie active) ◆ Three chip enables for simple depth expansion ◆ Single 3.
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