FEATURES
x 256K x 36, 512K x 18 memory configurations x Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) x ZBTTM Feature - No dead cycles between write and read cycles x Internally synchronized output buffer enable eliminates the need to control OE x Single R/W (READ/WRITE) control pin x 4-word burst capability (Interleaved or linear) x Individual byte write (BW1 - BW4) control (May tie active) x Three chip enables for simple depth expansion x 3.3V power supply (±5%) x 3.3V (±5%) I/O Supply (VDDQ) x Power down controlled by ZZ input x Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA). DESCRIPTION
They are designed to eliminate
IDT
