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IDT8P34S1212I - 1:12 LVDS Output 1.8V Fanout Buffer

Datasheet Summary

Description

The IDT8P34S1212I is a high-performance differential LVDS fanout buffer.

The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals.

The IDT8P34S1212I is characterized to operate from a 1.8V power supply.

Features

  • 12 low skew, low additive jitter LVDS output pairs.
  • Two selectable, differential clock input pairs.
  • Differential CLK0, CLK1 pairs can accept the following differential input levels: LVDS, CML.
  • Maximum input clock frequency: 1.2GHz (maximum).
  • LVCMOS/LVTTL interface levels for the control input select pin.
  • Output skew: 10ps (typical).
  • Propagation delay: 340ps (typical).
  • Low additive phase jitter, RMS; fREF = 156.25MHz, VPP =.

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Datasheet Details

Part number IDT8P34S1212I
Manufacturer IDT
File Size 534.77 KB
Description 1:12 LVDS Output 1.8V Fanout Buffer
Datasheet download datasheet IDT8P34S1212I Datasheet
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Full PDF Text Transcription

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1:12 LVDS Output 1.8V Fanout Buffer IDT8P34S1212I Datasheet Description The IDT8P34S1212I is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The IDT8P34S1212I is characterized to operate from a 1.8V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the IDT8P34S1212I ideal for those clock distribution applications that demand well-defined performance and repeatability. Two selectable differential inputs and 12 low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.
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