IDT8P34S1212I Datasheet | IDT

1:12 LVDS Output 1.8V Fanout Buffer IDT8P34S1212I Datasheet Description The IDT8P34S1212I is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The IDT8P34S1212I is characterized to operate from a 1.8V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the IDT8P34S1212I ideal for those clock distribution applications that demand well-defined performance and repeatability. Two selectable differential inputs and 12 low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise. Block Diagram VDD CLK0 nCLK0 fREF VDD CLK1 nCLK1 SEL VREF VREF Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7 Q8 nQ8 Q9 nQ9 Q10 nQ10 Q11 nQ11 SEL CLK1 nCLK1 nc VDD VDD VREF nCLK0 CLK0 nc Features - 12 low skew, low additive jitter LVDS output pairs - Two selectable, differential clock input pairs - Differential CLK0, CLK1 pairs can accept the following differential input levels: LVDS, CML - Maximum input clock frequency: 1.2GHz (maximum)...