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SSTE32882KB1 - 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER

Description

This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation.

All inputs are 1.25,1.35V and 1.5V CMOS compatible, except the reset (RESET) and MIRROR inputs which are LVCMOS.

Features

  • Pinout optimizes DDR3 RDIMM PCB layout.
  • DDR3-800/1066/1333/1600/1866/2133 rate.
  • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs.
  • Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four differential outputs.
  • Supports LVCMOS switching levels on the RESET and MIRROR inputs.
  • Checks priority on DIMM-independent data inputs.
  • Supports dynamic 1T/3T timing.

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Datasheet Details

Part number SSTE32882KB1
Manufacturer IDT
File Size 887.36 KB
Description 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER
Datasheet download datasheet SSTE32882KB1 Datasheet
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Full PDF Text Transcription

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DATASHEET 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT SSTE32882KB1 Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation. All inputs are 1.25,1.35V and 1.5V CMOS compatible, except the reset (RESET) and MIRROR inputs which are LVCMOS. All outputs are 1.25V,1.35V and 1.5V CMOS edge-controlled drivers optimized to drive single terminated 25 to 50 traces in DDR3 RDIMM applications, except the open-drain error (ERROUT) output. The clock outputs (Yn and Yn) and control net outputs QnCKEn, QnCSn and QnODTn are designed with a different strength and skew to compensate for different loading and equalize signal travel speed.
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