SSTE32882KB1 Datasheet | IDT

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation. All inputs are 1.25,1.35V and 1.5V CMOS patible, except the reset (RESET) and MIRROR inputs which are LVCMOS. All outputs are 1.25V,1.35V and 1.5V CMOS edge-controlled drivers optimized to drive single terminated 25 to 50 traces in DDR3 RDIMM applications, except the open-drain error (ERROUT) output. The clock outputs (Yn and Yn) and control net outputs Qn CKEn, Qn CSn and Qn ODTn are designed with a different strength and skew to pensate for different loading and equalize signal travel speed. The SSTE32882KB1 has two basic modes of operation associated with the Quad Chip Select Enable (QCSEN) input. When the QCSEN input pin is open (or pulled high), the ponent has two chip select inputs, DCS0 and DCS1, and two copies of each chip select output, QACS0, QACS1, QBCS0 and QBCS1. This is the "Quad CS disabled" mode. When the QCSEN input pin is pulled low, the ponent has four chip select inputs DCS[3:0], and four chip select outputs, QCS[3:0]. This is the "Quad CS enabled" mode. Through the remainder of this specification, DCS[n:0] will indicate all of the chip select inputs, where n=1 for Quad CS disabled, and n=3 for Quad CS enabled. Qx CS[n:0] will indicate all of the chip select outputs. DRAS, DCAS, and DWE), and indicates whether a parity error has occurred on the open-drain ERROUT pin (active low). The convention is even parity; i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs bined with the parity input bit. To calculate parity, all DIMM-independent D-inputs must be tied to a known logic state. The DIMM-dependent signals (DCKEn, DODTn, and DCSn) are not included in the parity check putation. To ensure defined outputs from the register before a stable...