Overview: IMP5111/5112 DATA MUNICATIONS 9-Line SCSI Terminator
– 35MHz Channel Bandwidth
The 9-channel IMP5111/5112 SCSI terminator is part of IMP's family of high-performance SCSI terminators that deliver true UltraSCSI performance. The BiCMOS design offers superior performance over first generation linear regulator/resistor based terminators.
IMP's new architecture employs high-speed adaptive elements for each channel, thereby providing the fastest response possible - typically 35MHz, which is 100 times faster than the older linear regulator terminator approach. The bandwidth of terminators based on the older regulator/resistor terminator architecture is limited to 500kHz since a large output stabilization capacitor is required. The IMP architecture eliminates the external output pensation capacitor and the need for transient output capacitors while maintaining pin patibility with first generation designs. Reduced ponent count is inherent with the IMP5111/5112.
The IMP5111/5112 architecture tolerates marginal system designs. A key improvement offered by the IMP5111/5112 lies in its ability to insure reliable, error-free munications even in systems which do not adhere to remended SCSI hardware design guidelines, such as improper cable lengths and impedance. Frequently, this situation is not controlled by the peripheral or host designer.
For portable and configurable peripherals, the IMP5111/5112 can be placed in a sleep mode with a disconnect signal. Quiescent current is less than 275µA when disabled. When disabled, the outputs are in a high impedance state with output capacitance less than 3pF.
