IMP5225 Datasheet | IMP

Description section). The IMP architecture eliminates the output pensation capacitor required in linear regulator/ resistor designs. The IMP5225 architecture tolerates marginal system designs. A key improvement offered by the IMP5225 lies in its ability to insure reliable, error-free munications even in systems which do not adhere to remended SCSI hardware design guidelines, such as the use of improper cable lengths and impedances. Frequently, this situation is not controlled by the peripheral or host designer. The IMP5225 has two disconnect pins for SCSI Plug and Play (Pn P) applications. To enter the disconnect mode, the disconnect pins must be driven LOW thereby disconnecting the IMP5225 from the SCSI bus. Quiescent current is less than 150µA when disabled. Reduced ponent count is inherent in the IMP5225 architecture. Traditional termination techniques require large stabilization and Key Features x SCSI Plug and Play - Dual active LOW disconnect pins x Ultra-Fast response for Fast-20 SCSI x 35MHz channel bandwidth x Sleep-mode current less than 150µA - Disconnects terminator from lows x NO external pensation capacitors x patible with active negation drivers x patible with passive and active terminations x Approved for use with SCSI 1, 2, 3 and Ultra SCSI x Hot swap patible x Pin-for-pin patible with LX5225, LX5205 and UC5607 transient protection capacitors of up to 20µF in value and size. The IMP5225 architecture does not require these ponents, allowing all the cost savings associated with inventory, board space, assembly, reliability, and ponent costs. The IMP5225 is a superior pin-for-pin replacement for the LX5225, LX5205, UC5607. Block Diagrams VTERM Term Power Current Biasing Circuit 24m A Current Limiting Circuit 2.85V DATA OUTPUT PIN DB (0) DISCONNECT 1 DISCONNECT 2 Enable Logic VTERM 0.4V - + Daily Silver IMP .ds-imp..cn 1 of 18 Channels 5225_01.eps Pin Configuration SOWB-28 DISCONNECT 1 1 28 DISCONNECT 2 T1 2 27 T18 T2 3 26...