IS42S16100F Overview
The synchronous DRAMs achieve highspeed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. Available for IS42S16100F only.
IS42S16100F Key Features
- Clock frequency
- Fully synchronous; all signals referenced to a positive clock edge
- Two banks can be operated simultaneously and independently
- Dual internal bank controlled by A11 (bank select)
- Single power supply: IS42/45S16100F: Vdd/Vddq = 3.3V IS42VS16100F: Vdd/Vddq = 1.8V
- LVTTL interface
- Programmable burst length
- (1, 2, 4, 8, full page)
- Programmable burst sequence: Sequential/Interleave
- 2048 refresh cycles every 32 ms
