IS43DR81280C ISSI Datasheet

IS43DR81280C Key Features

• Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
• JEDEC standard 1.8V I/O (SSTL_18-patible)
• Double data rate interface: two data transfers per clock cycle
• Differential data strobe (DQS, DQS)
• 4-bit prefetch architecture
• On chip DLL to align DQ and DQS transitions with CK
• 8 internal banks for concurrent operation
• Programmable CAS latency (CL) 3, 4, 5, 6 and 7 supported
• Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, 5 and 6 supported
• WRITE latency = READ latency