IS43LR16200D Overview
Key Specifications
Package: TFBGA
Operating Voltage: 1.8 V
Max Voltage (typical range): 1.95 V
Min Voltage (typical range): 1.7 V
Description
The IS43LR16200D is 33,554,432 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 2 banks of 1,048,576 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation.
Key Features
- JEDEC standard 1.8V power supply
- Two internal banks for concurrent operation
- MRS cycle with address key programs
- CAS latency 2, 3 (clock)
- Burst length (2, 4, 8
