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IS43LR32100C - 512K x 32Bits x 2Banks Mobile DDR SDRAM

Download the IS43LR32100C datasheet PDF. This datasheet also covers the IS46LR32100C variant, as both devices belong to the same 512k x 32bits x 2banks mobile ddr sdram family and are provided as variant models within a single manufacturer datasheet.

General Description

The IS43/46LR32100C is 33,554,432 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 2 banks of 524,288 words x 32 bits.

This product uses a double-data-rate architecture to achieve high-speed operation.

Key Features

  • JEDEC standard 1.8V power supply.
  • Two internal banks for concurrent operation.
  • MRS cycle with address key programs - CAS latency 2, 3 (clock) - Burst length (2, 4, 8, 16) - Burst type (sequential & interleave).
  • Fully differential clock inputs (CK, /CK).
  • All inputs except data & DM are sampled at the rising edge of the system clock.
  • Data I/O transaction on both edges of data strobe.
  • Bidirectional data strobe per byte of data (DQS).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS46LR32100C-ISSI.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by ISSI (now Infineon)

Part Number Description
IS43LR32100D 512K x 32Bits x 2Banks Mobile DDR SDRAM
IS43LR32160B 4M x 32Bits x 4Banks Mobile DDR SDRAM
IS43LR32160C 4M x 32Bits x 4Banks Mobile DDR SDRAM
IS43LR32200B 512K x 32Bits x 4Banks Mobile DDR SDRAM
IS43LR32200C 512K x 32Bits x 4Banks Mobile DDR SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS43LR32100C IS46LR32100C 512K x 32Bits x 2Banks Mobile DDR SDRAM Description The IS43/46LR32100C is 33,554,432 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 2 banks of 524,288 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve high bandwidth. All input and output voltage levels are compatible with LVCMOS. Features • JEDEC standard 1.