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IS43R83200B - 256Mb DDR Synchronous DRAM

Key Features

  • Vdd =Vddq = 2.5V+0.2V (-5, -6, -75).
  • Double data rate architecture; two data transfers per clock cycle.
  • Bidirectional , data strobe (DQS) is transmitted/ received with data.
  • Differential clock input (CLK and /CLK).
  • DLL aligns DQ and DQS transitions with CLK transitions edges of DQS.
  • Commands entered on each positive CLK edge;.
  • Data and data mask referenced to both edges of DQS.
  • 4 bank operation controlled by BA0 ,.

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Other Datasheets by ISSI (now Infineon)

Part Number Description
IS43R83200D DDR SDRAM
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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IS43R83200B, IS46R83200B IS43R16160B, IS46R16160B 32Mx8, 16Mx16 256Mb DDR Synchronous DRAM AUGUST 2010 FEATURES: • Vdd =Vddq = 2.5V+0.2V (-5, -6, -75) • Double data rate architecture; two data transfers per clock cycle. • Bidirectional , data strobe (DQS) is transmitted/ received with data • Differential clock input (CLK and /CLK) • DLL aligns DQ and DQS transitions with CLK transitions edges of DQS • Commands entered on each positive CLK edge; • Data and data mask referenced to both edges of DQS • 4 bank operation controlled by BA0 , BA1 (Bank Address) • /CAS latency -2.0 / 2.5 / 3.