IS46LD32800A Overview
AUGUST 2017 The IS43/46LD16160A/32800A is 256Mbit CMOS LPDDR2 DRAM. The device is organized as 4 banks of 4Meg words of 16bits or 2Meg words of 32bits. This product uses a double-data-rate architecture to achieve high-speed operation.
IS46LD32800A Key Features
- High Speed Un-terminated Logic(HSUL_12) I/O Interface
- Clock Frequency Range : 10MHz to 533MHz (data rate range : 20Mbps to 1066Mbps per I/O)
- Four-bit Pre-fetch DDR Architecture
- Multiplexed, double data rate, mand/address inputs
- Four internal banks for concurrent operation
- Bidirectional/differential data strobe per byte of data (DQS/DQS#)
- Programmable Read/Write latencies(RL/WL) and burst lengths(4,8 or 16)
- ZQ Calibration
- On-chip temperature sensor to control self refresh rate
- Partial -array self refresh(PASR)