IS46LD32320A Description
The deviceis organized as 8 banks of 8Meg words of 16bits or 4Meg words of 32bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins.
IS46LD32320A Key Features
- High Speed Un-terminated Logic(HSUL_12) I/O Interface
- Clock Frequency Range : 10MHz to 400MHz (data rate range : 20Mbps to 800 Mbps per I/O)
- Four-bit Pre-fetch DDR Architecture
- Multiplexed, double data rate, mand/address inputs
- Eight internal banks for concurrent operation
- Bidirectional/differential data strobe per byte of data (DQS/DQS#)
- Programmable Read/Write latencies(RL/WL) and burst lengths(4,8 or 16)
- Per-bank refresh for concurrent operation
- ZQ Calibration
- On-chip temperature sensor to control self refresh rate