Datasheet4U Logo Datasheet4U.com

IS46TR16640ED - 1Gb DDR3 SDRAM

Download the IS46TR16640ED datasheet PDF. This datasheet also covers the IS43TR16640ED variant, as both devices belong to the same 1gb ddr3 sdram family and are provided as variant models within a single manufacturer datasheet.

General Description

RAS#.

CAS#.

Key Features

  • Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V.
  • High speed data transfer rates with system frequency up to 800 MHz.
  • 8 internal banks for concurrent operation.
  • 8n-bit pre-fetch architecture.
  • Programmable CAS Latency.
  • Programmable Additive Latency: 0, CL-1,CL-2.
  • Programmable CAS WRITE latency (CWL) based on tCK.
  • Programmable Burst Length: 4 and 8.
  • Programmable Burst Sequence: Sequential or Interleave.
  • BL switch on the fly.
  • Auto Self Refresh(A.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS43TR16640ED-ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS46R16160F 256Mb DDR SDRAM Integrated Silicon Solution
IS46R16320D 16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM Integrated Silicon Solution
IS46R16320E 512Mb DDR SDRAM Integrated Silicon Solution
IS46R16800E 128Mb DDR SDRAM Integrated Silicon Solution
IS46R32160D 16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS46TR16640B 1Gb DDR3 SDRAM
IS46TR16640BL 1Gb DDR3 SDRAM
IS46TR16128B 2Gb DDR3 SDRAM
IS46TR16128BL 2Gb DDR3 SDRAM
IS46TR16128C 2Gb DDR3 SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS43/46TR16640ED IS43/46TR81280ED 128MX8, 64MX16 1Gb DDR3 SDRAM WITH ECC FEATURES  Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V  High speed data transfer rates with system frequency up to 800 MHz  8 internal banks for concurrent operation  8n-bit pre-fetch architecture  Programmable CAS Latency  Programmable Additive Latency: 0, CL-1,CL-2  Programmable CAS WRITE latency (CWL) based on tCK  Programmable Burst Length: 4 and 8  Programmable Burst Sequence: Sequential or Interleave  BL switch on the fly  Auto Self Refresh(ASR)  Self Refresh Temperature(SRT) ECC  Single bit error correction (per 64-bits)  Restrictions on Burst Length and Data Mask OPTIONS  Configuration: 128Mx8 64Mx16  Package: 96-ball FBGA (9mm x 13mm) for x16 78-ball FBGA (8mm x 10.