IS61DDP2B21M36C1 Datasheet | ISSI

IS61DDP2B22M18C/C1/C2 IS61DDP2B21M36C/C1/C2 2Mx18, 1Mx36 36Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM (2.0 Cycle Read Latency) JANUARY 2017 Features DESCRIPTION - 1Mx36 and 2Mx18 configuration available. - mon I/O read and write ports. - Max. 500 MHz clock for high bandwidth - Synchronous pipeline read with self-timed late write operation. - Double Data Rate (DDR) interface for read and write input ports. The 36Mb IS61DDP2B21M36C/C1/C2 and IS61DDP2B22M18C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a mon I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are selftimed....